Current trends in the semiconductor industry include faster switching speeds, reduced power consumption, and lower operating voltages, wherein the performance of MOS transistors needs to be correspondingly improved. For example, high-speed transistors are required for modern wireless communications systems, portable computers, and other low-power, low-voltage devices, wherein MOS transistors must be adapted to operate at lower voltages using less power. Carrier mobility in a MOS transistor has a significant impact on power consumption and switching performance. The carrier mobility is a measure of the average speed of a carrier (e.g., holes or electrons) in a given semiconductor, given by the average drift velocity of the carrier per unit electric field. Improving the carrier mobility in the channel region of a MOS transistor can improve the switching speed, and can also facilitate operation at lower voltages, alone or in combination with reducing the transistor channel length and gate dielectric thickness to improve current drive and switching performance.
Carrier mobility of a MOS transistor is affected by the mechanical stress in the device channel. The carrier mobility can be improved by depositing silicon/germanium alloy or other material layers between upper and lower silicon layers under compressive stress, in order to enhance hole carrier mobility in a channel region. For NMOS transistors, tensile stress in the channel material improves carrier mobility by lifting conduction band degeneracy. However, buried silicon/germanium channel layer devices have shortcomings, including increased alloy scattering in the channel region that degrades electron mobility, a lack of favorable conduction band offset which mitigates the enhancement of electron mobility, and the need for large germanium concentrations to produce strain and thus enhanced mobility. Furthermore, such additional alloy layers and silicon layers are costly, adding further processing steps to the device manufacturing procedure.
Thus, there is a need for methods and apparatus by which the carrier mobility and other electrical operational properties of MOS transistor devices may be improved so as to facilitate improved switching speed and low-power, low-voltage operation, without significantly adding to the cost or complexity of the manufacturing process.